1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and more particularly to a manufacturing method of a MIM type capacitor.
2. Description of Related Art
The memory cell of the dynamic random access memory (DRAM) comprises a selective transistor and a capacitor and with miniaturization of the memory cell accompanying a progress of fine processing technology, reduction in the charge accumulation quantity of the capacitor has been problematic. To solve this problem, researches for transforming the capacitor structure from metal insulator silicon (MIS) structure to metal insulator metal (MIM) structure with increasing an electrode surface area by fabricating a solid capacitor have been performed aggressively. Particularly, the MIM type capacitor using ruthenium (Ru) film as its electrode has attracted public attention as technology for mass production because ruthenium film chemical vapor deposition (CVD) technology and processing technology have advanced rapidly.
FIG. 2 is a longitudinal sectional view showing a typical conventional example of a memory cell having the MIM type capacitor. Two selective transistors are formed in an active region provided by sectioning the main surface of a silicon substrate 10 with a separating insulating film 2. Each selective transistor comprises a gate electrode 4 formed through a gate insulating film 3 on the main surface of the silicon substrate 10 and a pair of diffusion layer regions 5, 6 served as a source region and a drain region and the diffusion layer region 5 of the respective selective transistors is integrated and commonly used. In this selective transistor, a bit line 8 formed on interlayer insulation films 25, 26 and the diffusion layer region 5 are connected through a polysilicone plug 12 and a metal plug 7 which run through the interlayer insulation film 25. The bit line 8 is covered with the interlayer insulation film 21 and a capacitor is formed by laminating ruthenium film 41 as a lower electrode, ruthenium film 61 as an upper electrode and tantalum oxide film 51 as a capacity insulation film in a hole provided in the interlayer insulation film 22 formed on the interlayer insulation film 21. The lower electrode 41 is connected to a barrier metal film 32 on its bottom face and the barrier metal film 32 is connected to the polysilicone plug 11 through its bottom face via a contact metal film 31 and further, the polysilicone plug 11 is connected to the diffusion layer region 6 of the transistor through the polysilicone plug 12 located below. A first layer wiring 86 is formed on the ruthenium film 61 as the upper electrode and the first wiring 86 and the ruthenium film 61 are connected through a connection plug 81 formed by penetrating the interlayer insulation film 27.
A first conventional example of the manufacturing method of the MIM type capacitor in a memory cell shown in FIG. 2 will be described with reference to FIGS. 3–14. After a contact hole penetrating an interlayer insulation film 21 is filled with polysilicone film, a polysilicone plug 11 is formed by etching back (FIG. 3). Titan film and titan nitride film 32 acting as a barrier metal film are formed in a recess portion on the top face of the polysilicone plug 11. After that, titan silicide film 31 is formed by reacting the titan film with polysilicone through heat treatment in the atmosphere of nitrogen. Subsequently, the barrier metal film out of the recess is removed according to chemical mechanical polishing (CMP) method (FIG. 4). Next, the interlayer insulation film 22 is formed and a cylinder hole 92 penetrating the interlayer insulation film 22 is formed so as to expose the surface of the barrier metal film 32 on the bottom face of the cylinder hole 92 (FIG. 5).
Next, ruthenium film 41 is formed as a lower electrode according to spattering method and CVD method (FIG. 6). Then, photo resist film 99 is formed in the hole (FIG. 7) and the ruthenium film existing on the top portion of the hole is removed by etching back while protecting the ruthenium film in the hole (FIG. 8) and the lower electrode 41 is obtained by removing the photo resist film 99 (FIG. 9). Next, tantalum oxide film 51 is formed according to the CVD method and heat treatment is carried out to reform the tantalum oxide film 51 (FIG. 10). Subsequently, ruthenium film 61 is formed as an upper electrode according to the spattering method and CVD method (FIG. 11). This ruthenium film 61 is processed to the shape of the upper electrode according to photo lithography technology and dry etching technology (FIG. 12), and the interlayer insulation film 27 is formed (FIG. 13). The interlayer insulation film 27 is formed according to plasma CVD method using tetraethyl orthosilicate (TEOS) and oxygen (O2) as material gas. Although this method has prevailed because the interlayer insulation film (SiO2 film) can be formed at low cost and at low temperatures (≦400° C.), a cavity 95 is formed in the upper electrode because of insufficient coverage.
The ruthenium film is material of precious metal easy to process by dry etching and can be etched for example, in the atmosphere of oxygen, or mixture gas of chlorine and oxygen. However, if the ruthenium film is used as the lower electrode, it is partially oxidized during etching processing, thereby inducing a problem that leaks current increases. That is, if when part of the lower electrode turns to oxide of ruthenium, capacity insulation film is formed thereon, the oxide of ruthenium is altered, deformed or contracted during heat treatment for reformation of the capacity insulation film and as a consequence, stress is applied to the capacity insulation film thereby increasing leak current.
Japanese Unexamined Patent Publication (KOKAI) No.2001-313379 has described a method in which a second ruthenium film 43 serving as a buffer film (protective film) is grown selectively on the surface of a first ruthenium film 41 after the first ruthenium film is processed into the shape of the lower electrode, as a method for preventing increase in leak current originating from oxide of ruthenium. This method has attained a certain extent of effect in that deterioration of leak current characteristic of a capacitor originating from oxide on the surface of ruthenium film of the lower electrode is prevented (FIG. 14).
However, according to the conventional example shown in FIG. 14, although the increase in leak current originating from oxide on the surface of the lower electrode is prevented, an increase in leak current originating from oxidation of the upper electrode cannot be prevented. That is, although part of the ruthenium film is altered to oxide during etching processing of the upper electrode, the oxide is reduced to ruthenium film again in a process accompanying heat treatment in a reduction atmosphere after the formation of the capacitor. Because contraction of the volume occurs so that the density of the upper electrode is lowered, reduction gas permeates the ruthenium film of the upper electrode to reduce the tantalum oxide film and hydrogen is contained in the tantalum oxide film. As a result, there occur such problems that leak current increases.